FIG. 8 depicts noise reduction technology in a conventional semiconductor device (for example, see Patent Document 1). An internal circuit 110 in a semiconductor device 100 is an internal circuit which includes a circuit operating in synchronization with a clock signal, and is schematically depicted in FIG. 8 by a buffer 111 to which a clock signal CLK is inputted. The internal circuit 110 is supplied with a power supply potential VDD by a VDD power supply line 103 and supplied with a reference potential VSS by a VSS power supply line 104.
When an output of the internal circuit 110 is switched, high-frequency noise due to switching is generated in the power supply lines 103, 104 to which the internal circuit 110 is coupled. The generated noise is propagated through the power supply lines 103, 104 and is propagated to power supply lines 105, 106 of the outside via terminals 101, 102.
Conventionally, a low-pass filter (LPF) 120 is provided in a path through which generated noise is propagated, to restrain the noise from being propagated outside. The LPF 120 is constituted, as depicted in an example of FIG. 8, with a capacitance 121 coupled between the VDD power supply line 103 and the VSS power supply line 104 in the semiconductor device 100, for example.
Further, in order to carry out a noise suppression effectively, there is suggested a simulation method in which noise generated from an integrated circuit may be evaluated in a stage of a circuit design or a layout design of the integrated circuit (for example, see Patent Document 2).
Patent Document 1: Japanese Laid-open Patent Publication No. 08-102525
Patent Document 2: Japanese Laid-open Patent Publication No. 11-120214